Experience AI at 61DAC 

The exponential rise of AI is disrupting the electronic design industry. There's no better place to learn about the importance of AI in chips to system design than at DAC.

Explore the full program to discover the latest technologies that are driving innovation in the world of chip design. #61DAC has more educational session submissions than ever before, and the program committee is placing an emphasis on the future of AI for chip design.

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See all highlighted sessions below.

*Requires Full Conference registration in order to attend the session or activity.

** Requires Engineering Track registration in order to attend the session or activity. 

Sunday, June 23

DCgAA 2024: International Workshop on DL-Hardware Co-Design for Generative AI Acceleration*

Workshop | 8:00 a.m. – 12:00 p.m. PT

GREAT: Gen-AI Research in Electronic Design, Automation, and Test*

Workshop | 1:00 p.m. – 5:00 p.m. PT

How Will AI Drive EDA and IP Growth

Analyst Presentation | 5:00 p.m. – 6:00 p.m. PT

 

Monday, June 24

Keynote Presentation with Jim Keller

Keynote Presentation | 9:00 a.m. – 9:45 a.m. PT

AI co-pilot: Exploring the AI Frontier in Chip Design**

Front End Design Session | 10:30 a.m. – 12:00 p.m. PT

Design and Synthesis of Certifiably Safe AI-enabled Autonomy with Focus on Human-in-the-Loop Human-in-the Plant Systems*

Tutorial | 1:30 p.m. – 5:00 p.m. PT

 

Tuesday, June 25

Charting a Course to Navigate Irregular Data Access in Graph Neural Networks and Beyond!*

Research Sessions | 10:30 a.m. – 12:00 p.m. PT

• DEFA: Efficient Deformable Attention Acceleration via Pruning-Assisted Grid-Sampling and Multi-Scale Parallel Processing
• Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse
• GDR-HGNN: A Heterogeneous Graph Neural Networks Accelerator with Graph Decoupling and Recouping
• SC-GNN: A Communication-Efficient Semantic Compression for Distributed Training of GNNs
• CDA-GNN: A Chain-driven Accelerator for Efficient Asynchronous Graph Neural Network
• RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference

Empowering Edge Intelligence: When IoT Devices Meet AI*

Research Sessions | 10:30 a.m. – 12:00 p.m. PT

• Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems
• LEAF: An Adaptation Framework against Noisy Data on Edge through Ultra Low-Cost Training
• Deep Harmonic Finesse: Signal Separation in Wearable Systems with Limited Data
• EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
• RT-MDM: Real-Time Scheduling Framework for Multi-DNN on MCU Using External Memory
• Go Beyond Black-box Policies: Rethinking the Design of Learning Agent for Interpretable and Verifiable HVAC Control

The Open Chiplet Economy and AI**

IP Presentation | 10:30 a.m. – 12:00 p.m. PT

The evolution of the Digital Twin for Semiconductor and how AI will expand Manufacturing Aware Design

TechTalk Presentation | 11:15 a.m. – 12:00 p.m. PT

New EDA Methodologies are Transforming Engineering Lifecycle Management

SKYTalk Presentation | 1:00 p.m. – 1:45 p.m. PT

AI Technologies Meet Quantum Computing*

Special Sessions | 1:30 p.m. – 3:00 p.m. PT

• Machine Learning for Optimization of Quantum Compilation
• Graph Learning for Parameter Prediction of Quantum Approximate Optimization Algorithm
• Challenges and Opportunities of Quantum Optimization in Finance

Asleep at the Wheel? In-Cabin Monitoring for Automotive Safety.**

Research Panel | 1:30 p.m. – 3:00 p.m. PT

Efficient Acceleration Strategies for Transformers: From Token Similarity to Weight Sparsity*

Research Sessions | 1:30 p.m. – 3:00 p.m. PT

• CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration
• FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA
• FNM-Trans: Efficient FPGA-based Transformer Architecture with Full N:M Sparsity
• ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm
• SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering
• Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation

The Next Step to Efficient AI: Number Formats, Quantization and Beyond*

Research Sessions | 1:30 p.m. – 3:00 p.m. PT

• Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
• Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers
• RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers
• APTQ: Attention-aware Post-Training Mixed-Precision Quantization for Large Language Models
• EDGE-LLM: Enabling Efficient Large Language Model Adaptation on Edge Devices via Unified Compression and Adaptive Layer Voting

AutoDV: AI-Generated HDL with Design Verification In-The-Loop

Exhibitor Forum Presentation | 3:30 p.m. – 4:00 p.m. PT

What is the Future of Design Verification? UVM, PSS, Formal, VIP, AI & Beyond**

Front End Design Session | 3:30 p.m. – 5:00 p.m. PT

AI Efficiency From Far Memory to Cross-Platform Performance*

Research Sessions | 3:30 p.m. – 5:00 p.m. PT

• Sharry：An Efficient and Sharing Far Memory System
• PowerLens: An Adaptive DVFS Framework for Optimizing Energy Efficiency in Deep Neural Networks
• Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision
• Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device Modeling
• A Holistic Functionalization Approach to Optimizing Imperative Tensor Programs in Deep Learning
• Crop: An Analytical Cost Model for Cross-Platform Performance Prediction of Tensor Programs
• G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning
• SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks

Generative AI for Chip Design: Game Changer or Damp Squib?**

Research Panel | 3:30 p.m. – 5:00 p.m. PT

Where Analog, Digital, and ML/AI Meet! *

Research Sessions | 3:30 p.m. – 5:00 p.m. PT

• CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging
• VAE-HDC: Efficient and Secure Hyper-dimensional Encoder Leveraging Variation Analog Entropy
• Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology Design
• ChatCPU: An Agile CPU Design and Verification Platform with LLM
• Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning
• AdderNet 2.0: Optimal FPGA Acceleration of AdderNet with Activation-Oriented Quantization and Fused Bias Removal based Memory Optimization
• CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis
• ZeroTetris: A Spacial Feature Similarity-based Sparse MLP Engine for Neural Volume Rendering

 

Wednesday, June 26

AI and the Intelligent Edge

Keynote Presentation | 9:00 a.m. – 9:45 a.m. PT

AI Paradigms beyond Deep Neural Networks*

Research Sessions | 10:30 a.m. – 12:00 p.m. PT

• Zeroth-Order Optimization of Optical Neural Networks with Linear Combination Natural Gradient and Calibrated Model
• Order-Preserving Cryptography for the Confidential Inference in Random Forests: FPGA Design and Implementation
• SMORE: Similarity-Based Hyperdimensional Domain Adaptation for Multi-Sensor Time Series Classification
• Leanor: A Learning-Based Accelerator for Efficient Approximate Nearest Neighbor Search via Reduced Memory Access
• GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration
• Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

Edge Intelligence & GenAI: Exploring Challenges and Ethics**

Embedded Systems and Software Session | 10:30 a.m. – 12:00 p.m. PT

Industry Trends in the Front End**

Front End Design Sessions | 10:30 a.m. – 12:00 p.m. PT

• AI-Powered High-Sigma Automated Full Library Verification Methodology for Standard Cells
• Improving Power Efficiency using Workload-aware PPA Analysis for AI Engine
• Augmenting IP/SOC Verification Exhaustiveness with BER Transformer infused Deep Learning Model
• Shift Left Detection and Root Cause Analysis of Synthesis Optimized Registers at RTL Level
• Design Constraint Strategy For Dealing With Cascaded Clock MUX Structures

Optimizing Both Directions: Better AI Algorithm for Systems and Better Systems for AI*

Research Sessions | 10:30 a.m. – 12:00 p.m. PT

• MoteNN: Memory Optimization via Fine-grained Scheduling for Deep Neural Networks on Tiny Devices
• Garrison: A High-Performance GPU-Accelerated Inference System for Adversarial Ensemble Defense
• AdaptiveFL: Adaptive Heterogeneous Federated Learning for Resource-Constrained AIoT Systems
• Enabling Multi-Tensor Fused Dataflow for Transformer Models on Spatial Accelerators
• HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI
• Auto-ISP: An Efficient Real-Time Automatic Hyperparameter Optimization Framework for ISP Hardware System

Why Is EDA Playing Catchup to Disruptive Technologies Like AI? What Can We Do to Change This?**

Research Panel | 10:30 a.m. – 12:00 p.m. PT

Revolutionizing Edge Autonomy with Cognitive Multispectral Sensing*

Special Sessions | 10:30 a.m. – 12:00 p.m. PT

• Overview of Cognitive Multispectral Sensing
• Enabling AI-based Sensing with 5G Networks at the Edge
• Lightweight Uncertainty Quantification at the Edge: Know When Your AI model Doesn't
• Internet of Bodies for Seamless Human-Machine Co-operation and Real-time AI

Do-More-with-Less: Optimizing AI Models for Inference Efficiencies*

Research Sessions | 1:30 p.m. – 3:00 p.m. PT

• PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference
• Deep Reorganization: Retaining Residuals in TinyML
• GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference
• On the Design of Novel Attention Mechanism for Enhanced Efficiency of Transformers
• INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding
• MoC: A Morton-Code-Based Fine-Grained Quantization for Accelerating Point Cloud Neural Networks

Embedded Systems and Software**

Embedded Systems and Software Sessions | 1:30 p.m. – 3:00 p.m. PT

• No-Code Power and Clock System Design
• Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
• Complex application mapping to heterogeneous compute resources
• Automated Generation of SSD Stress Tests Using Offline Reinforcement Learning
• Development of SystemC-based Security VP for In-House SED SSD Firmware Verification and Application of libFuzzer
• Open Source AUTOSAR Classic Platform

Large Language Model - Revolutionizing the Entire Computing Paradigm*

Special Sessions | 1:30 p.m. – 3:00 p.m. PT

• Large Language Models (LLM) for HLS Optimization and Verification
• HDL-GPT: High Quality HDL Is All You Need
• LLM4AIGChip: Harnessing Large Language Models Towards Automation of AI Accelerator Design

Glitz, Glam, and Binary Jam: A Symphony of New Security Trends for Deep Neural Networks** Research Sessions | 3:30 p.m. – 5:30 p.m. PT

• TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments
• Older and Wise: The Marriage of Device Aging and Intellectual Property Protection of DNNs
• QMark: Robust Watermarks for IP Protection of Quantized Large Language Models
• AdvHunter: Detecting Adversarial Perturbations in Black-Box Neural Networks through Hardware Performance Counters
• DNN-Defender: A Victim-Focused In-DRAM Defense Mechanism for Taming Adversarial Weight Attack on DNNs
• Defending against Adversarial Patches using Dimensionality Reduction
• EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks
• FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference

 

Thursday, June 27

Complexity Matters: Scheduling and Accelerating Data Structures in DNNs*

Research Sessions | 10:30 a.m. – 12:00 p.m. PT

• E-DGCN: An Efficient Architecture Design for Accelerating Dynamic Graph Convolutional Network (DGCN) Inference
• EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization
• Fused Sampling and Grouping with Search Space Reduction for Efficient Point Cloud Acceleration
• A Software-Hardware Co-design Solution for 3D Inner Structure Reconstruction
• A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems
• FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing

It's Not 8b Retro-Gaming, It's State-Of-The-Art Architectures Using Quantization, Sparsity, and Compression!*

Research Sessions | 10:30 a.m. – 12:00 p.m. PT

• Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation
• Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration
• MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy
• DySpMM: From Fix to Dynamic for Sparse Matrix-Matrix Multiplication Accelerators
• Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access
• SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs

Foundation Models for EDA and Beyond*

Research Sessions | 1:30 p.m. – 3:30 p.m. PT

• Automatically Fixing RTL Syntax Errors with Large Language Model
• Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model
• ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours
• Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
• Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS
• TrafficHD: Efficient Hyperdimensional Computing for Real-Time Network Traffic Analytics
• VARADE: a Variational-based AutoRegressive model for Anomaly Detection on the Edge
• ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization

 

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