2024 TechTalk Speakers
The Evolution of the Digital Twin in Semiconductor Design and the Central Role AI Plays
Tuesday, June 25 | 11:15 am - 12:00 pm
Abstract: Depending on who you talk with the Digital Twin is either the newest thing in semiconductor, or something that semiconductor has always had. The truth is that both are true. Semiconductor has long relied on domain specific Digital Twins of different aspects of the design in order to design, test, and integrate in the virtual world before committing to manufacture. Starting with the Siemens acquisition of EDA, but now being talked about more widely, we now talk about the Comprehensive Digital Twin of the design, which attempts to more completely capture the design and allow analysis using not only traditional EDA but also Multiphysics. This is just the beginning however, as we are already moving towards the merging of the Design Digital Twin, with the Manufacturing Digital Twin to enable closed loop manufacturing aware design.
This evolution brings with it new challenges of exponentially increasing complexity, and multiple disparate engineering domains that need to work together. It is here where AI is coming to the rescue to help guide where engineers need to focus their effort, encapsulate domain knowledge that they need to perform a task, and transform data between different domains either directly or via surrogate models.
In this presentation we will explore the way this evolution has affected IC and product design tools, the benefits it has brough to design teams, what the future holds, and how closed-loop manufacturing aware design will bring in a new era of design.
About: Juan C. Rey, vice-president of government programs, previous vice president of Engineering, Calibre, joined Mentor in 2001 as senior engineering director for Mentor’s industry-leading Calibre product line, directing all development activities for Calibre products.
Previously he was vice-president of Engineering at Exend Corporation, managing all software development and quality activities. Prior to that he was engineering director for Physical Verification at Cadence Design Systems.
Earlier positions include: manager/developer for Process Modeling and Parasitic Extraction at Technology Modeling Associates; visiting scholar/science and engineering associate at Stanford University; senior research engineer at INVAP, Argentina; and associate professor at Universidad Nacional del Comahue, Argentina.
Juan holds a degree in Nuclear Engineering from Instituto Balseiro, Universidad Nacional de Cuyo, Argentina. The author or co-author of numerous papers and conference presentations, he serves on the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and previously at the SI2 Board of Directors and the Industry Advisory Board of the UCLA Center for Domain-Specific Computing.
2024 Analysts
A View from Wall Street
Monday, June 24 | 10:15 am - 11:00 am
We will examine the financial performance and key business metrics of the EDA industry through 2023, as well as the material technical and market trends and requirements that have influenced EDA business performance and strategies. Among the trends, we will again examine the progression of semiconductor R&D spending and how the market value of the publicly held EDA companies has evolved. Lastly, we will provide our updated financial projections for the EDA industry for 2024 through 2026.
ABOUT: Mr. Vleeschhouwer has over four decades of research experience. He is a senior industry analyst covering Engineering and Enterprise Software, responsible for fundamental research of companies under coverage, including the regular publication of proprietary company and industry reports and detailed company and industry financial modeling. Principal industry reports include The Software Standard (software industry commentary, news, data, and analysis) and The State of EDA (quarterly in-depth review of electronic design automation). Ranked by Refinitiv Starmine Analyst Awards (U.S.) #1 in "top stock pickers" for software (2020). He has been regularly invited to present at software and other industry conferences, in addition to broadcast media appearances and other print and online media
Designing an ASIC for the Generative AI Era
Tuesday, June 25 | 10:15 am - 11:00 am
The presentation will cover what is required to design an ASIC for the Generative AI Era. It will cover the compute, networking, and memory constraints of generative AI as well as what companies are doing to push beyond it with optics, packaging, and system level design.
ABOUT: Dylan Patel is the founder and Chief Analyst of SemiAnalysis, a semiconductor and AI research company. SemiAnalysis has analysts across the US, Japan, Taiwan, Singapore, and France covering the industry from production of materials, equipment, process technology, fabs to design IP and fabless to physical infrastructe of datacenters, networking, and AI models.
Chiplets - The Next Generation Chip Design Trend Beyond Moore's Law
Wednesday, June 26 | 10:15 am - 11:00 am
The next stage of integrated circuit manufacturing is disaggregation or breaking up the design of large chips into smaller units. These smaller units typically represent a unique function. The advantages are shorter design time, lower cost, easier drop-in inclusion of already available designs, increased modularity and scalability, and fewer manufacturing defects. This technique is especially well suited for leveraging the heterogeneous nature of large processors, coprocessors, system on chip (SoC) and integrated memory solutions, but the evolution of this trend is likely to spread throughout IC design.
This presentation is designed to provide a brief introduction to the nature of chiplet design and why it is so important at this time. The technical details will be presented in moderation including teardown examples of current chiplet solutions and which end-systems include them. The presentation will touch on technology advances that need to evolve to facilitate this approach. We will provide a market penetration and a five-year forecast for chiplet-based design strategies. We will provide longer views of the evolution to include such ICs as graphics, AI, and other accelerators, FGPAs, microcontrollers and other processors. We will conclude with why we think this trend is essential to the future of the semiconductor industry and design automation.
ABOUT:
Tom Hackenberg is a Principal Analyst for Computing and Software in the Semiconductor, Memory and Computing Division at Yole Intelligence, part of Yole Group. Tom is an industry leading expert reporting on markets for semiconductor processors including CPUs, MPUs, MCUs and DSPs, SoCs, GPUs and discrete accelerators, FPGAs, and configurable processors since 2006. Tom is also well-versed in related technology trends including AI and edge computing, IoT, heterogeneous processing, chiplets, as well as vertical markets like Automotive, Computing and Telecommunications where processor trends play a significant role.
Tom has appeared as a presenter on these topics at associated events as the Chiplet Summit, OCP ODAS Workshop on Chiplets, Rosenblatt’s Age of AI Scaling, System-on-Chip Conference, Vision and AI Summit, Xilinx Adapt: Automotive: Anywhere, Yole’s Live Market Briefings and as well as custom proprietary presentations. He can also be found quoted or bylined in news and trade publications such as Cision, Computerworld, Design and Reuse, EE|Times & EE|Times Asia, Fierce Electronics, Insider, Semi Engineering, VentureBeat, and more for expertise on the processor market.
Tom worked with market-leading processor suppliers developing both syndicated and custom research. He holds a BSEE/BSECE from the University of Texas at Austin specializing in Processors and FPGAs.